TCAD CENTRAL TCAD CENTRALWelcome to the leading independent source of TCAD news andinformation.Apr 12, 1999Mar 5, 1999Nov 2, 1998Jun 22, 1998Jan 16, 1999///Feb 11, 1999Jan 5, 1999A is now online.(April 12, 1999)The 3rd NASA Ames Device Modeling Workshop is planned for August. It will include a session on CMOS Devices at the End of the Roadmap.Thanks to the PISCES-for-Win32 beta testers (especially Dave Clark). For theexecutable, graciously provided by the late-night efforts ofJavascript Disabled.This program will run under 32bit Windows operating systems on X86architectures, including Win95/Win98/WinNT. They are 'naive' ports in that theyrun best from a command line environment (MS-DOS window).
Dragging the icon ofa PISCES input file in Windows Explorer and dropping it on the PISCES icondoesn't work. MINIMOS6 on the horizon. (Mar 15, 1999).Roy Jewell left Avant! Earlier this week. I believe he is retired fromTCAD. (Mar 5, 1999)added to Calibration page.
Semiconductor TCAD Fabrication Development for BCD Technology A Major Qualifying Project Report: submitted to the Faculty of the WORCESTER POLYTECHNIC INSTITUTE in partial fulfillment of the requirements for the Degree of Bachelor of Science by Matthew Hazel Marc Cyr Date: March 13, 2006. Advantage of TCAD to analyze RF-LDMOS for the broadband power amplifier Abstract: Technology Computer Aided Design (TCAD) provides an alternate method to study the power amplifier (PA) design prior to fabrication and is very useful for the extraction of an accurate large signal model.
(Mar 5, 1999)Here is the final agenda for the conference. (Feb 11, 1999)If you'd like to be informed ofwhen there are significant changes to this web site, Javascript DisabledThis site last updated April 12, 1999 byJavascript Disabled, whose professional goal is to increase theuse of TCAD in technology development and in education.Disclaimer: All opinions expressed here are personal, anddo not represent the opinions of any company or university. Noconfidential information should be shared. All company/productsnames are trademarks/registered trademarks of their respectiveholders.
There is no tracking of who visits this site.to my old office (Fab25).
Harmonic Balance Device Analysis of an LDMOS RF Power Amplifierwith Parasitics and Matching Network Harmonic Balance Device Analysis of an LDMOS RF Power Amplifierwith Parasitics and Matching NetworkIntroductionIn order to accelerate the design phase of new devices, simulation tools provide valuable insight into performance.For RF devices, Stanford and HP jointly developed an harmonic balance simulator for analyzing a device in thefrequency domain1. However, the performance of this RF device is not restricted to intrinsic effects and can dependupon parasitics from interconnect and packaging as well as the matching networks and bias circuitry used to connectthe device to the rest of the circuit. This paper addresses the RF simulation of the external circuit components inconjunction with the intrinsic device. The paper describes a simulation approach and presents an example of practicalimportance to industry.Device and Circuit StructureThe device under analysis is a LDMOS structure from Motorola 23. A laterally diffused graded channelenhances RF performance, prevents punch-through, and increases the device transconductance. A p+ sinker connectssource and substrate together to eliminate extra bond wires and provide for a back side contact. An LDD decreasesthe electric field at the drain and a metal field plate reduces the electric fields at the edge of the gate.Surrounding the device are a large number of circuit parasitics represented in block diagram form in.
Nearestthe intrinsic device are the parasitics from interconnect resistances and capacitances. From the package, bond wiresinclude inductances and outside the package, the bias circuitry and matching networks establish a connection to therest of the circuit. The biasing circuitry is isolated from the input/output by inductors which block high frequencieswhile the matching networks are isolated with capacitors which block DC. Show the experimental andsimulated IV characteristics for the device.The device operates with up to 6V on the gate and 20V on the drain. Theexperimental Ids vs. Vds curves match the PISCES simulation using a local mobility model developed at Stanford4.Under high gate and drain biases, a high current generates heat, thus reducing the mobility; however, the device israrely operated in this region.
Shows the good agreement for the Id vs. Vg curves in the linear region(Vd=0.1V) and saturations region (Vd=6.0V).Simulation Tool StructureStanford and HP jointly developed a PISCES extension that solves the semiconductor equations in the frequencydomain thus enabling large signal sinusoidal simulations. However, circuit aspects from parasitics to matchingnetworks play an important role in the actual utilization of the device.To include the circuit components in the device simulation they are reduced to a set of boundary condition equations.shows a PISCES device surrounded by an arbitrary linear network.
By assuming unknown voltages andcurrents at the electrodes of the device, the relationship among those voltages and currents are computed(refer to given Equation). For large signal AC analysis, the boundary conditions become complex and are calculated at eachfrequency. The Vapplied vector contains the source vector at DC and the fundamental frequencies. It is zero for thegenerated harmonics since the surrounding circuity is linear and hence, generates no new harmonics.Circuit boundary conditions and harmonic balance simulation is integrated with PISCES as shown in.PISCES calls the circuit boundary condition routines to generate the equations from a SPICE like netlist. It then callsthe harmonic balance solver passing the boundary conditions and PISCES state variables.
The harmonic balancesolver uses the PISCES assembly routines to generate the Jacobian and RHS at each frequency for each iteration.Once the convergence criteria is met, the solution is passed back to PISCES which calls a circuit solver to get thecomplete solution.Simulation ResultsThis simulation algorithm is applied to the Motorola device to analyze its RF performance at 850MHz. The keydesign criteria are the power gain and the power added efficiency as shown in. The gain rolls off at higherpower levels (Pin 15dbm) because the device is operating in the gm compression region and the output power is limited by the saturation current. The efficiency is low for a smallPin because the device drains more power in class A operation. Efficiencyincreases until just after the gain starts to decrease.
At this point, Pin approaches Pout resulting in very little poweradded to the input signal. The simulation results in qualitatively follow the experimental results.
Furthertuning of the mobility models will improve the agreement.ConclusionHarmonic balance device simulation is a powerful tool for analyzing many types of RF problems. Coupling thedevice simulation with circuit parasitics and circuitry, extends the capabilities of the simulator to include not only thephysical device but also an extrinsic components that ultimately affect the performance of the structure. This paperdemonstrates the power of the tool by analyzing an LDMOS RF power transistor for gain and efficiency givenparasitics, bias circuitry, and matching networks.References. B. Troyanovsky, F. Dutton, and J. 'Large Signal Analysis of RF/MicrowaveDevices with Parasitics Using Harmonic Balance Device Simulation.'
Fukuoka, Japan: Nov. 1996. Gordon Ma, Wayne Burger, Chris Dragon, and Todd Gillenwater. 'High Efficiency LDMOS Power FET for LowVoltage Wireless Communications.'
Proceedings of IEDM. San Francisco, CA: December 1996. Alan Wood, Chris Dragon, and Wayne Burger.
'High Performance Silicon LDMOS Technology for 2GHz RFPower Amplifier Applications.' Proceeding of IEDM. San Francisco, CA: December 1996. A. Mujtaba, S.-I. Takagi, and R.
'Accurate modeling of Coulombic scattering, and its impact on scaledMOSFETs.' Technical Digest of Symposium on VLSI Technology.
Kyoto, Japan: June 1995.Figure 1: LDMOS device cross section.Figure 2: Block diagram of amplifier circuit includingbiasing and matching network.Figure 3: Simulated and experimental draincharacteristics.Figure 4: Simulated and experimental gate characteristics.Figure 5: PISCES device surrounded by an arbitrarylinear circuit.Figure 6: Integration of PISCES with linearcircuit BC's and harmonic balance.Figure 7: Experimental values for power gainand power added efficiency.Figure 8: Simulated values for power gain andpower added efficiency.